The present invention relates to a surface computer and a computing method capable of performing fast computation in various types of complex computations, such as physical computation, environmental computation, behavior computation, computations for emotional expressions and the like by concurrently computing computation data contained in a two-dimensional region in units of two-dimensional regions.
Recently, various fields of natural science and engineering have remarkably progressed. In natural science and engineering, large-scale physical computation is required. For example, large-scale matrix computation must be performed in the fields of space development projects, fluid dynamics, and quantum mechanics. When such computation is desired to be performed at high speed, a computer must be optimized.
Conventional computers, particularly personal computers, have progressed enough to exceed outdated general-purpose computers (so-called xe2x80x9cmainframesxe2x80x9d).
However, it is difficult for such personal computers to perform the above-described large-scale computation at high speed, or the personal computers take a long time to carry out the above computations. As reasons which prevent the personal computers from performing the large-scale computation at high speed, delays in data transfer speed, data processing speed, and the like which occur in the computers can be considered.
Therefore, among developers, researchers, and the like who must perform the above large-scale physical computations, computers which can perform large-scale computation at high speed have long been desired.
Accordingly, it is an object of the present invention to provide a computer having a novel architecture and a computing method using the same capable of performing large-scale computation at high speed.
To this end, according to a first aspect of the present invention, there is provided a surface computer including an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.
According to a second aspect of the present invention, a surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region, a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers and a storage unit connected to the concurrent computer.
According to a third aspect of the present invention, a surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region, and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers, wherein the region specified by an operand constituting an instruction word is a line.
According to a fourth aspect of the present invention, a surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region, and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers, wherein the region specified by an operand constituting an instruction word is a surface region extending two-dimensionally.
According to a fifth aspect of the present invention, a surface computer includes a data bus, having a large bus width, allowing a processing block and a storage block formed in one chip to be connected therebetween. In the surface computer, the processing block includes an address generator for generating an address for adjusting surface region data concerning a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers, and the storage block includes DRAM.
According to a sixth aspect of the present invention, in a surface computer includes an address generator, a processing block having a concurrent computer comprising a plurality of unit computers, a storage block, a data bus having a large bus width and allowing the processing block and the storage block to be connected therebetween, the computing method includes an address generating step for causing the address generator to generate an address for adjusting surface region data concerning a storage region, and a processing step for causing the concurrent computer to process the surface region data.